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Features
* Single-voltage Operation * * * * * * * * *
- 5V Read - 5V Reprogramming Fast Read Access Time - 55 ns Internal Program Control and Timer 16-Kbyte Boot Block with Lockout Fast Erase Cycle Time - 10 seconds Byte-by-byte Programming - 50 s/Byte Hardware Data Protection DATA Polling for End of Program Detection Low Power Dissipation - 50 mA Active Current - 100 A CMOS Standby Current Typical 10,000 Write Cycles
Description
The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 A. The device contains a user-enabled "boot block" protection feature. The AT49F040 locates the boot block at lowest order addresses ("bottom boot"). (continued)
4-megabit (512K x 8) 5-volt Only Flash Memory AT49F040
Pin Configurations
Pin Name A0 - A18 CE OE WE I/O0 - I/O7 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs
DIP Top View
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
TSOP Top View Type 1
A11 A9 A8 A13 A14 A17 WE VCC A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
PLCC Top View
4 3 2 1 32 31 30 A12 A15 A16 A18 VCC WE A17 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 14 15 16 17 18 19 20 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7
Rev. 0998D-03/01
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To allow for simple in-system reprogrammability, the AT49F040 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F040 is performed by erasing the entire 4 megabits of memory and then programming on a byte-by-byte basis. The byte programming time is a fast 50 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
VCC GND OE WE CE DATA INPUTS/OUTPUTS I/O7 - I/O0 8 OE, CE, AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING 7FFFFH X DECODER MAIN MEMORY (496K BYTES) OPTIONAL BOOT BLOCK (16K BYTES) 04000H 03FFFH 00000H
Y DECODER ADDRESS INPUTS
Device Operation
READ: The AT49F040 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 512K bytes memory array (or 496K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical "1". The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical "0") on a byte-by-byte basis. Please note that a data "0" cannot be 2 programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 03FFFH.
AT49F040
AT49F040
Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F040 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F040 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F040 in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
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Command Definition (in Hex)
Command Sequence Read Chip Erase Byte Program Boot Block Lockout(1) Product ID Entry Product ID Exit
(2)
Bus Cycles 1 6 4 6 3 3 1
1st Bus Cycle
Addr Data
2nd Bus Cycle
Addr Data
3rd Bus Cycle
Addr Data
4th Bus Cycle
Addr Data
5th Bus Cycle
Addr Data
6th Bus Cycle
Addr Data
Addr 5555 5555 5555 5555 5555 XXXX
DOUT AA AA AA AA AA F0 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 5555 5555 5555 5555 5555 80 A0 80 90 F0 5555 Addr 5555 AA DIN AA 2AAA 55 5555 40 2AAA 55 5555 10
Product ID Exit(2) Notes:
1. The 16K byte boot sector has the address range 00000H to 03FFFH. 2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT49F040
AT49F040
DC and AC Operating Range
AT49F040-55 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 5V 10% AT49F040-70 0C - 70C -40C - 85C 5V 10% AT49F040-90 0C - 70C -40C - 85C 5V 10% AT49F040-12 0C - 70C -40C - 85C 5V 10%
Operating Modes
Mode Read Program(2) Standby/Write Inhibit Program Inhibit X Output Disable Product Identification A1 - A18 = VIL, A9 = VH,(3) A0 = VIL A1 - A18 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A18 = VIL A0 = VIH, A1 - A18 = VIL Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) X VIL VIH CE VIL VIL VIH X OE VIL VIH X(1) X WE VIH VIL X VIH X X High Z Ai Ai Ai X I/O DOUT DIN High Z
Hardware
VIL
VIL
VIH
Software(5)
Notes:
1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V. 4. Manufacturer Code: 1FH, Device Code: 13H. 5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC(1) VIL VIH VOL VOH1 VOH2 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC Com. CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Ind. Min Max 10 10 100 300 3 50 0.8 Units A A A A mA mA V V V V V
Note:
1. In the erase mode, ICC is 90 mA.
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AC Read Characteristics
AT49F040-55 Symbol tACC tCE
(1) (2)
AT49F040-70 Min Max 70 70 0 0 0 35 25
AT49F040-90 Min Max 90 90 0 0 0 40 25
AT49F040-12 Min Max 120 120 0 0 0 50 30 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 55 55
tOE
0 0 0
30 25
tDF(3)(4) tOH
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. 2. 3. 4.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
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AT49F040
AT49F040
AC Byte Load Characteristics
Symbol tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 50 0 0 90 50 0 90 Max Units ns ns ns ns ns ns ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
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Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 90 90 10 Min Typ 10 Max 50 Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
OE must be high only when WE and CE are both low.
8
AT49F040
AT49F040
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time
0
ns
Notes:
1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time
(2)
Min 10 10
Typ
Max
Units ns ns ns
150 0
ns ns
Notes:
1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. 2. 3.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.
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Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION (2)(3)(5) MODE
Boot Block Lockout Feature Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION (4) MODE
Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION (4) MODE OR
LOAD DATA 40 TO ADDRESS 5555
PAUSE 1 second
(2)
Notes for boot block lockout feature enable: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled.
Notes for software product identification: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A18 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 13H
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AT49F040
AT49F040
AT49F040 Ordering Information
tACC (ns) 55 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49F040-55JC AT49F040-55PC AT49F040-55TC AT49F040-55JI AT49F040-55PI AT49F040-55TI AT49F040-70JC AT49F040-70PC AT49F040-70TC AT49F040-70JI AT49F040-70PI AT49F040-70TI AT49F040-90JC AT49F040-90PC AT49F040-90TC AT49F040-90JI AT49F040-90PI AT49F040-90TI AT49F040-12JC AT49F040-12PC AT49F040-12TC AT49F040-12JI AT49F040-12PI AT49F040-12TI Package 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
0.3
70
50
0.1
0.3
90
50
0.1
0.3
120
50
0.1
0.3
Package Type 32J 32P6 32T 32-lead, Plastic, J-leaded Chip Carrier Package (PLCC) 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-lead, Thin Small Outline Package (TSOP)
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Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
32P6, 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
.045(1.14) X 45
PIN NO. 1 IDENTIFY
.025(.635) X 30 - 45 .012(.305) .008(.203) .530(13.5) .490(12.4) .021(.533) .013(.330) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05)
1.67(42.4) 1.64(41.7)
PIN 1
.032(.813) .026(.660)
.553(14.0) .547(13.9) .595(15.1) .585(14.9)
.566(14.4) .530(13.5)
.050(1.27) TYP
.300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS
1.500(38.10) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18)
.090(2.29) MAX .005(.127) MIN
.022(.559) X 45 MAX (3X) .453(11.5) .447(11.4) .495(12.6) .485(12.3)
.110(2.79) .090(2.29)
.065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5)
.065(1.65) .015(.381) .022(.559) .014(.356)
.012(.305) .008(.203)
32T, 32-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BA
INDEX MARK
18.5(.728) 18.3(.720)
20.2(.795) 19.8(.780)
0.50(.020) BSC
7.50(.295) REF 8.20(.323) 7.80(.307)
0.25(.010) 0.15(.006)
1.20(.047) MAX
0.15(.006) 0.05(.002) 0 5 REF 0.20(.008) 0.10(.004) 0.70(.028) 0.50(.020)
*Controlling dimension: millimeters
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AT49F040
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(c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Marks bearing
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0998D-03/01/xM

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